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INTEGRATED CIRCUITS
74F112 Dual J-K negative edge-triggered flip-flop
Product specification IC15 Data Handbook 1990 Feb 09
Philips Semiconductors
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
FEATURE
* Industrial temperature range available (-40C to +85C)
DESCRIPTION
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn. TYPE 74F112 TYPICAL PROPAGATION DELAY 100MHz
PIN CONFIGURATION
CP0 K0 J0 SD0 Q0 Q0 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD0 RD1 CP1 K1 J1 SD1 Q1
SF00103
TYPICAL SUPPLY CURRENT (TOTAL) 15mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F112N N74F112D INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F112N I74F112D PKG DWG # SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS J0, J1 K0, K1 SD0, SD1 RD0, RD1 CP0, CP1 Q0, Q0; Q1, Q1 J inputs K inputs Set inputs (active Low) Reset inputs (active Low) Clock Pulse input (active falling edge) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/5.0 1.0/5.0 1.0/4.0 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/3.0mA 20A/3.0mA 20A/2.4mA 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
February 9, 1990
2
853-0338 98775
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
LOGIC SYMBOL
3 11 2 12
IEC/IEEE SYMBOL
3 1 1J C1 1K R S 6 5
1 4 15 13 10 14
J0 CP0 SD0 RD0 CP1
J1
K0 K1
2 15 4
11 SD1 RD1 Q0 Q0 Q1 Q1 13 12 14 10 VCC = Pin 16 GND = Pin 8 5 6 9 7
2J C2 2K R S 7 9
SF00104
SF00105
LOGIC DIAGRAM
5, 9 Qn
6, 7 Qn
4, 10 SDn 2, 12 Kn
15, 14 RDn 3, 11 Jn
VCC = Pin 16 GND = Pin 8
1, 13 CPn
SF00106
FUNCTION TABLE
INPUTS SD L H L H H H H H RD H L L H H H H H CP X X X H J X X X h l h l X K X X X h h l l X OUTPUTS Q H L H* q L H q Q Q L H H* q H L q Q Asynchronous Set Asynchronous Reset Undetermined * Toggle Load "0" (Reset) Load "1" (Set) Hold "no change" Hold "no change" OPERATING MODE
H = High voltage level h = High voltage level one setup time prior to High-to-Low clock transition L = Low voltage level l = Low voltage level one setup time prior to High-to-Low clock transition q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition X = Don't care = High-to-Low clock transition * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
February 9, 1990
3
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Commercial range Operating free-air temperature range free air Storage temperature range Industrial range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -40 to +85 -65 to +150 UNIT V V mA V mA C C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Commercial range Operating free-air temperature range free air Industrial range 0 -40 PARAMETER MIN 4.5 2.0 0.8 -18 -1 20 +70 +85 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Jn, Kn IIL IOS Low-level input current current3 CPn SDn, RDn Short-circuit output VCC = MAX -60 VCC = MAX, VI = 0.5V VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.5 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 -2.4 -3.0 -150 V A A mA mA mA mA V TYP2 MAX UNIT
VO OH
High-level High level output voltage
V
VO OL VIK II IIH
ICC Supply current (total)4 VCC = MAX 15 21 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, with the Q and Q outputs High in turn.
February 9, 1990
4
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
AC ELECTRICAL CHARACTERISTICS
LIMITS TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF RL = 500 MIN fMAX tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CP to Qn or Qn Propagation delay SDn, RD to Qn or Qn Waveform 1 Waveform 1 Waveform 2,3 85 2.0 2.0 2.0 2.0 TYP 100 5.0 5.0 4.5 4.5 6.5 6.5 6.5 6.5 MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF RL = 500 MIN 80 2.0 2.0 2.0 2.0 7.5 7.5 7.5 7.5 MAX VCC = +5.0V 10% Tamb = -40C to +85C CL = 50pF RL = 500 MIN 80 2.0 2.0 1.5 1.5 7.5 7.5 7.5 7.5 MAX MHz ns ns
SYMBOL
PARAMETER
UNIT
AC SETUP REQUIREMENTS
LIMITS TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF RL = 500 MIN tS(H) tS((L) th(H) th(L) tW(H) tW(L) tW(L) tREC Setup time, High or Low Jn, Kn to CP Hold time, High or Low Jn, Kn to CP CP Pulse width High or Low SDn, RD Pulse width Low Recovery time SDn, RD to CP Waveform 1 Waveform 1 Waveform 1 Waveform 2,3 Waveform 2,3 4.0 3.5 0.0 0.0 4.5 4.5 4.5 4.5 TYP MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF RL = 500 MIN 5.0 4.0 0.0 0.0 5.0 5.0 5.0 5.0 MAX VCC = +5.0V 10% Tamb = -40C to +85C CL = 50pF RL = 500 MIN 5.0 4.0 0.0 0.0 5.0 5.0 5.0 5.0 MAX ns ns ns ns ns
SYMBOL
PARAMETER
UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V.
Jn, Kn VM ts(L) VM th(L) fmax CPn VM tw(L) VM tw(H) tPLH Qn VM tPHL Qn VM VM tPHL VM ts(H) VM th(H)
VM tPLH VM
SF00107
The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width
February 9, 1990
5
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
Jn, Kn
SDn
VM
tw(L) VM tREC
CPn
VM
tPLH Qn VM tPHL Qn VM
SF00108
Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock
Jn, Kn
RDn
VM
tw(L) VM tREC
CPn tPHL Qn VM tPLH Qn VM
VM
SF00109
Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock
February 9, 1990
6
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
February 9, 1990
7
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1990 Feb 09
8
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1990 Feb 09
9
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05071
Philips Semiconductors
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